Related entries include:
16 bit; 32-bit application; 3DNow!; 3DNow! Professional; 64-bit; Adaline; address space; ANSI/SPARC Architecture; architecture; asynchronous; asynchronous logic; Axiomatic Architecture Description Language; Basic Object Adapter; bit slice; bus; bus master; Byzantine; Cache On A STick; cellular multiprocessing; Cellular Neural Network; central processing unit; cloud computing; CNN; cognitive architecture; control bus; Core Protocol Stack; Data Address Generator; data bus; data feed; data flow; data path; delayed control-transfer; direct mapped cache; Direct Memory Access; distributed memory; DNA computing; Dynamic Address Translation; dynamic translation; emulation; endian; Extended Industry-Standard Architecture; fault tolerance; fetch-execute cycle; first generation computer; flat address space; Flynn's taxonomy; fourth generation computer; Harvard architecture; hit rate; IA32; Industry Standard Architecture; input; Instruction Address Register; instruction prefetch; instruction set; instruction set architecture; Intelligent Input/Output; Java Virtual Machine; little-endian; main memory; Many Integrated Core Architecture; memory address space; memory mapped I/O; Memory Type Range Registers; Micro Channel Architecture; microlog; microprocessor; middle-endian; Moore's Law; nanocomputer; Next Program Counter; Non-Uniform Memory Access; northbridge; NUXI problem; orthogonal instruction set; output; overflow bit; page in; page out; ping-pong; pipeline; pipeline break; Portable Object Adapter; PowerPC Platform; power save mode; prepaging; primary cache; Redundant Array of Independent Disks; Redundant Array of Inexpensive Servers; Richard P. Feynman; second generation computer; segmented address space; sequential processing; serial processor; service-oriented architecture; set associative cache; single program/multiple data; southbridge; SSE-2; stack pointer; state; Streaming SIMD Extensions; superscalar; systolic array; Task Control Block; third generation computer; three-tier; Translation Look-aside Buffer; Very Large Memory; Very Long Instruction Word; victim cache; virtual; von Neumann architecture; wait state; Web Service Definition Language; Windows Open Service Architecture; wintel; working memory; working set; write-through; XT bus architecture;
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